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final publication# 21020 rev: a amendment/ 0 issue date: april 1997 distinctive characteristics n member of the e86? cpu series C 16-bit data bus C 24-bit address bus C 16-mbyte address range C long-term stable supply from amd n 40-, 33- and 25-mhz operating speeds n ideal for embedded applications C true static design for low-power applications C 3C5 v operation (at 25 mhz) C ideal for cost-sensitive designs C true dc (0 mhz) operation n industry standard architecture C supports worlds largest software base for x86 architectures C wide range of chipsets and bios available C fully compatible with all 386sx systems and software n system management mode (smm) for system and power management (am386sxlv only) C system management interrupt (smi) for power management independent of processor operating mode and operating system C smi coupled with i/o instruction break feature provides transparent power off and auto resume of peripherals which may not be power aware C smi is non-maskable and has higher priority than non-maskable interrupt (nmi) C automatic save and restore of the microprocessor state n 100-lead plastic quad flat pack (pqfp) package n extended temperature version available general description the am386?sx/sxl/sxlv microprocessors are low- cost, high-performance cpus for embedded applica- tions. embedded customers benefit from using the am386 microprocessor in a number of ways. the am386sx/sxl/sxlv microprocessors provide embedded customers access to very inexpensive pro- cessors and the highest performance of any 386sx available anywhere. the 16-bit data path allows for in- expensive memory design. full static operation, cou- pled with 3-v supplies, benefit customers who desire low-power designs. standby mode allows the am386sxl/sxlv microprocessors to be clocked down to 0 mhz (dc) and retain full register contents. a float pin places all outputs in a three-state mode to fa- cilitate board test and debug. additionally, the am386sxlv microprocessor comes with system management mode (smm) for system and power management. smi (system management inter- rupt) is a non-maskable, higher priority interrupt than nmi and has its own code space (1 mbyte in real mode and 16 mbyte in protected mode). smi can be coupled with the i/o instruction break feature to imple- ment transparent power management of peripherals. smm can be used by system designers to implement system and power management code independent of the operating system or the processor mode. since the am386sx/sxl/sxlv microprocessors are supported as an embedded product in the e86 family, customers can rely on long-term supply of product, and extended temperature products. in addition, customers have access to the largest se- lection of inexpensive development tools, compilers, and chipsets. a large number of pc operating systems and real time operating systems (rtos) support the am386sx/sxl/sxlv microprocessors. this means cheaper development costs, and improved time to mar- ket. the am386sx/sxl/sxlv microprocessor is available in a small footprint 100-pin plastic quad flat pack (pqfp) package. am386 ? sx/sxl/sxlv high-performance, low-power, embedded microprocessors
2 am386sx/sxl/sxlv microprocessors data sheet final ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. ng sx speed option processor type sx = sx processor sxl = sx processor with static clock implementation sxlv = sxl processor with low-voltage and smi temperature range ng=100-lead plastic quad flat pack (pqb-100) processor family package type am386 family C40 = 40 mhz C33 = 33 mhz C25 = 25 mhz 80386 blank = commercial (t case = 0 c to +100 c) i = industrial (t case = C40 c to +100 c) i C40 valid combinations valid combinations lists configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. valid combinations ng80386 sx C25 C33 C40 sxl C25 C33 sxlv C25 ing80386 sx C25
final am386sx/sxl/sxlv microprocessors data sheet 3 block diagram functional description true static operation (am386sxl/sxlv only) the am386sxl/sxlv microprocessor incorporates a true static design. unlike dynamic circuit design, the am386sxl/sxlv device eliminates the minimum op- erating frequency restriction. it may be clocked from its maximum speed all the way down to 0 mhz (dc). sys- tem designers can use this feature to design portable applications with long battery life. standby mode (am386sxl/sxlv only) the true static design of the am386sxl/sxlv micro- processor allows for a standby mode. at any operating speed, the microprocessor will retain its state (i.e., the contents of all its registers). by shutting off the clock completely, the device enters standby mode. since power consumption is proportional to clock frequency, operating power consumption is reduced as the fre- quency is lowered. in standby mode, typical current draw is reduced to less than 20 microamps at dc. not only does this feature save battery life, but it also sim- plifies the design of power-conscious portable applica- tions in the following ways. n eliminates the need for software in bios to save and restore the contents of registers. n allows simpler circuitry to control stopping of the clock since the system does not need to know the state of the processor. lower operating icc (am386sxl/sxlv only) true static design also allows lower operating icc when operating at any speed. performance on demand (am386sxl/sxlv only) the am386sxl/sxlv microprocessor retains its state at any speed from 0 mhz (dc) to its maximum operat- ing speed. with this feature, system designers may vary the operating speed of the system to extend the battery life in portable systems. pipeline/ bus size control effective address bus effective address bus dedicated alu bus barrel shifter, adder multiply/ divide register file decode and sequencing control rom instruction decoder 3-decoded instruction queue prefetcher/ limit checker limit and attribute pla descriptor registers 3-input adder page cache adder request prioritizer address driver protection test unit alu control alu control instruction instruction code stream 32 32 32 25 32 segmentation unit paging unit bus control hold, intr, nmi, error , busy , reset, hlda, flt, smi *, iiben * bhe , ble , a23-a1 m/io , d/c , w/r , lock , ads , na , ready , smiads *, smirdy * d15-d0 * C on am386sxlv only 32 bit control attribute pla and prefetch predecode mux/ trans- ceivers status flags 16-byte code queue displacement bus physical address bus control code fetch/page table fetch linear address bus internal control bus 32
4 am386sx/sxl/sxlv microprocessors data sheet final for example, the system could operate at low speeds during inactivity or polling operations. however, upon interrupt, the system clock can be increased up to its maximum speed. after a user-defined time-out period, the system can be returned to a low (or 0 mhz) operat- ing speed without losing its state. this design maximiz- es battery life while achieving optimal performance. benefits of lower operating voltage (am386sxlv only) the am386sxlv microprocessor has an operating voltage range of 3.0 v to 5.5 v. low voltage allows for lower operating power consumption, longer battery life, and/or smaller batteries for portable applications. because power is proportional to the square of the volt- age, reduction of the supply voltage from 5.0 v to 3.3 v reduces power consumption by 56%. this directly translates to a doubling of battery life for portable appli- cations. lower power consumption can also be used to reduce the size and weight of the battery. thus, 3.3-v designs facilitate a reduction in the form factor. a lower operating voltage results in a reduction of i/o voltage swings. this reduces noise generation and provides a less hostile environment for board design. lower operating voltage also reduces electromagnetic radiation noise and makes fcc approval easier to ob- tain. smmsystem management mode (am386sxlv only) the am386sxlv microprocessor has a system man- agement mode (smm) for system and power manage- ment. this mode consists of two features: system management interrupt (smi) and i/o instruction break. smisystem management interrupt smi is implemented by using special bus interface pins. this interrupt method can be used to perform sys- tem management functions such as power manage- ment independent of processor operating mode (real, protected, or virtual 8086 modes). smi can also be invoked in software. this allows sys- tem software to communicate with smi power manage- ment code. in addition, the umov instruction allows data transfers between smi and normal system mem- ory spaces. activating the smi pin invokes a sequence that saves the operating state of the processor into a separate smm memory space, independent of the main system memory. after the state is saved, the processor is forced into real mode and begins execution at address fffff0h in the smm memory space where a far jump to the smm code is executed. this real mode code can perform its system management function and then resume execution of the normal system software by ex- ecuting an res3 instruction which will reload the saved processor state and continue execution in the main system memory space. see figure 1 for a general flow- chart of an smm operation. cpu interfacepin functions the cpu interface for smm consists of three pins ded- icated to the smi function. one pin, smi , is the interrupt input. the other two pins, smiads and smirdy , pro- vide the control signals necessary for the separate smm mode memory space. smi sampled active (low) current instruction finishes execution, normal ads goes inactive cpu saves state to sepa- rate smm memory space, starting at address 60000h cpu enters real mode, starts code fetches at location fffff0h in smm memory space real mode smm interrupt handler code execution (af- ter far jump) restore saved state from 60000h with res3 (0f 07) opcode sequence normal code execution resumes 16305cC002 figure 1. smm flow
final am386sx/sxl/sxlv microprocessors data sheet 5 description of smm operation (am386sxlv only) the execution of a system management interrupt has four distinct phases: the initiation of the interrupt via smi , a processor state save, execution of the smm in- terrupt code, and a processor state restore (to resume normal operation). interrupt initiation a system management interrupt is initiated by the driv- ing of a synchronous, active low pulse on the smi pin until the first smiads is asserted. this pulse period will ensure recognition of the interrupt. the cpu drives the smi pin active after the completion of the current oper- ation (active bus cycle, instruction execution, or both). the active drive of the pin by the cpu is released at the end of the interrupt routine following the last register read of the saved state. the cpu drives smi high for two clk2 cycles prior to releasing the drive of smi . an smi cannot be masked off by the cpu, and it will al- ways be recognized by the cpu, regardless of operat- ing modes. this includes the real, protected, and vir- tual-8086 modes of the processor. while the cpu is in smm, a bus hold request via the hold pin is granted . the hlda pin goes active after bus release and the smiads pin floats along with the other pins that normally float during a bus hold cycle. smi does not float during a bus hold cycle. processor state save the first set of smm bus transfer cycles after the cpus recognition of an active smi is the processor saving its state to an external ram array in a separate address space from main system memory. this is accom- plished by using the smiads and smirdy pins for ini- tiation and termination of bus cycles, instead of the ads and ready pins. the 24-bit addresses to which the cpu saves its state are 60000hC600cbh and 60100hC60127h. these are fixed address locations for each register saved. to ensure valid operation, pipelining must be disabled while the processor is in smm. there are 114 data transfer cycles. smi code execution after the processor state is saved to the separate smm memory space, the execution of the smm interrupt rou- tine code begins. the processor enters real mode, sets most of the register values to reset values (those values normally seen after a cpu reset), and begins fetching code from address fffff0h in the separate smm memory space. normally, the first thing the inter- rupt routine code does is a far jump to the real mode entry point for the smm interrupt routine, which is also in smm memory space. both intr and nmi are disabled upon entry into smm. the smm code can be located anywhere within the 1-mbyte real mode address space, except for where the processor state is saved. i/o cycles, as a result of the in, out, ins, and outs instructions, will go to the normal address space, utilizing the normal ads and ready bus interface signals. this facilitates power management code manipulating system hardware reg- isters as needed through the standard i/o subsystem; a separate i/o space is not implemented. processor state restore (resuming normal execution) returning to normal code execution in the main system memory, including restoring the processor operating mode, is accomplished by executing a special code se- quence. this code invokes a restore cpu state opera- tion that reloads the cpu registers from the saved data in the ram controlled by smiads and smirdy . the es:edi register pair must point to the physical ad- dress of the processor save state (6000h). in real mode the address is calculated as es?16 + edi offset. the saved state should not cross a 64k boundary. the res3 instruction (0f 07) should be executed to start the restore state operation. after completion of the re- store state operation, the smi pin will be deactivated by the cpu and normal code execution will continue at the point where it left off before the smi occurred. there are 114 data transfer cycles in the restore operation. software features (am386sxlv only) several features of the smi function provide support for special operations during the execution of the systems software. these features involve the execution of re- served opcodes to induce specific smi-related opera- tions. software smi generation besides hardware initiation of the smi via the smi pin, there is also a software-induced smi mechanism. gen- erating a soft smi involves setting a control bit (bit 12) in the debug control register (dr7) and executing an smi instruction (opcode f1h). the functional sequence of the software-based smi is identical to the hardware-based smi with the exception that the smi pin is not initially driven active by an exter- nal source. upon execution of a soft smi opcode, the smi pin is driven active (low) by the processor before the save state operation begins. memory transfers to main system memory while executing an smi routine, the interrupt code can initiate memory data reads and writes to the main sys- tem memory using the normal ads and ready pins. this initiation is accomplished by using reserved op- codes that are special forms of the mov instruction (called umov). the umov opcodes can move byte,
6 am386sx/sxl/sxlv microprocessors data sheet final word, or double word register operands to or from main system memory. multiple data transfers using the nor- mal ads and ready pins will occur if the operands are misaligned relative to the effective address used. the umov opcodes are 0f 10h, 0f 11h, 0f 12h, and 0f 13h. the umov instruction can use any of the 386 addressing modes, as specified in the modr/m byte of the opcode. note that the 16- and 32-bit versions are the same opcodes with the exception of the 66h oper- and size prefix. i/o instruction break (am386sxlv only) the am386sxlv microprocessor has an i/o instruc- tion break feature that allows the system logic to imple- ment i/o trapping for peripheral devices. to enable the i/o instruction break feature, iiben must first be as- serted active low. on detecting an i/o instruction, the processor prevents the execution unit from executing further instructions until ready is driven active low by the system. once ready is driven active, the execu- tion unit either immediately responds to any active in- terrupt request or continues executing instructions fol- lowing the i/o instruction that caused the break. the i/o instruction break feature can be used to allow system logic to implement i/o trapping for peripheral devices. on sensing an i/o instruction, the system drives the smi pin active before driving ready active. this ensures that the interrupt service routine is exe- cuted immediately following the i/o instruction that caused the break. (if the i/o instruction break feature is not enabled via iiben , several instructions could exe- cute before the smi service routine is executed.) the smi service routine can access the peripheral for which smi was asserted and modify its state.the smi service routine normally returns to the instruction fol- lowing the i/o instruction that caused the break. by modifying the saved state instruction pointer, the rou- tine can choose to return to the i/o instruction that caused the break and re-execute that instruction. the default is to return to the following instruction (except for rep i/o string instruction). to re-execute the i/o in- struction that caused the break, the smi service routine must copy the i/o instruction pointer over the default pointer. this feature is particularly useful when an ap- plication program requests an access to a peripheral that has been powered down. the smi service routine can restore power to the peripheral and initiate a re-ex- ecution sequence transparent to the application pro- gram. this re-execution feature should only be used if the smi is in response to an i/o trap with iiben active. note that the i/o instruction break feature is not en- abled for memory mapped i/o devices or for coproces- sor bus cycles even if iiben is active. i/o instruction break timing the i/o instruction break feature requires that smi be sampled active (low) by the processor at least three clk2 edges before the clk2 edge that ends the i/o cycle with an active ready signal. this timing applies for both pipelined and non-pipelined cycles. if this tim- ing constraint is not met, additional instructions may be executed by the internal execution unit prior to entering smm. depending on the state of the prefetch queue at the time the smi is asserted, instruction fetch cycles may occur on the normal ads interface before the smm save state process begins with the assertion of smiads . however, this fetched code will not be exe- cuted.
final am386sx/sxl/sxlv microprocessors data sheet 7 connection diagram 100-lead plastic quad flat pack (pqfp) packagetop side view ads 16 74 a19 nc 27 d0 1 v ss 2 hlda 3 hold 4 v ss 5 na 6 ready 7 v cc 8 v cc 9 v cc 10 v ss 11 v ss 12 v ss 13 v ss 14 clk2 15 ble 17 a1 bhe 19 nc 20 v cc 21 v ss 22 m/io 23 d/c 24 w/r 25 18 75 a20 73 a18 72 a17 71 v cc 70 a16 69 v cc 68 v ss 67 v ss 66 a15 65 a14 64 a13 63 v ss 62 a12 61 a11 60 a10 59 a9 58 a8 57 v cc 56 a7 55 a6 54 a5 53 a4 52 a3 51 a2 lock 26 flt 28 *iiben 29 *smirdy 30 *smiads 31 32 reset 33 busy 34 35 error 36 pereq 37 nmi 38 39 intr 40 41 42 *smi 43 nc 44 nc 45 nc 46 nc 47 48 49 50 d1 100 d2 99 98 97 d3 96 d4 95 d5 94 d6 93 d7 92 91 d8 90 d9 89 d10 88 d11 87 d12 86 85 84 d13 83 d14 82 d15 81 a23 80 a22 79 78 77 a21 76 notes : pin 1 is marked for orientation nc = not connected; connection of an nc pin may cause a malfunction or incompatibility with future shippings of the am386sx/sxl/sxlv microprocessors * = on am386sxlv only; nc on am386sx/sxl v cc v cc v cc v cc v ss v ss v ss v ss v ss v cc v cc v cc v ss v ss v ss top side view
8 am386sx/sxl/sxlv microprocessors data sheet final connection diagram 100-lead plastic quad flat pack (pqfp) packagepin side view 26 64 62 65 61 68 58 69 57 70 56 55 71 54 72 73 53 74 52 75 51 12 14 15 11 16 10 9 17 18 8 7 19 20 6 5 21 22 4 3 23 24 2 25 1 13 63 67 59 60 66 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 nc lock flt iiben * smirdy * smiads * reset busy error pereq nmi intr smi * nc nc nc nc v cc v cc v cc v cc v ss v ss v ss v ss ads d0 v ss hlda hold v ss na ready v cc v cc v cc v ss v ss v ss v ss clk2 ble a1 bhe nc v cc v ss m/io d/c w/r d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a23 a22 a21 v ss v cc v cc v cc v ss v ss v ss a19 a20 a18 a17 v cc a16 v cc v ss v ss a15 a14 a13 v ss a12 a11 a10 a9 a8 v cc a7 a6 a5 a4 a3 a2 notes : pin 1 is marked for orientation nc = not connected; connection of an nc pin may cause a malfunction or incompatibility with future shippings of the am386sx/sxl/sxlv microprocessors * = on am386sxlv only; nc on am386sx/sxl pin side view
final am386sx/sxl/sxlv microprocessors data sheet 9 pin designation table (sorted by functional grouping) pin designation table (sorted by pin number) 73 address data control nc v cc v ss a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a18 a20 a21 a22 a23 18 51 52 53 54 55 56 58 59 60 61 62 64 65 66 70 72 75 76 79 80 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 1 100 99 96 95 94 93 92 90 89 88 87 86 83 82 81 ads bhe ble busy clk2 error hlda hold intr lock na nmi pereq ready reset 16 19 17 34 15 24 36 28 3 4 40 26 23 6 38 37 7 33 25 20 27 44 45 46 47 8 9 10 21 32 39 42 48 57 69 71 84 91 97 2 5 11 12 13 14 22 35 41 49 50 63 67 68 77 78 85 98 d/c m/io flt pin name pin no. pin name pin no. pin name pin no. pin no. pin no. pin no. smi * smiads * smirdy * 43 31 30 iiben *29 w/r * on am386sxlv only; nc on am386sx/sxl a19 74 d0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 pin no. pin name 21 pin no. pin name 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 hlda hold na ready clk2 ads ble a1 bhe nc lock nc iiben * smirdy * smiads * reset busy error pereq nmi intr 41 pin no. pin name 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 smi * nc nc nc nc a2 a3 a4 a5 a6 a7 a8 a9 a10 61 pin no. pin name a11 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 81 pin no. pin name d15 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 v ss v ss v ss v ss v ss v ss v cc v cc v cc v ss v cc v cc v ss v cc m/io d/c w/r v ss v cc v cc v ss v ss v cc v ss v ss v cc v ss v ss v ss v cc v cc v cc v ss v cc v ss flt * on am386sxlv only; nc on am386sx/sxl
10 am386sx/sxl/sxlv microprocessors data sheet final pin descriptions a23Ca1 address bus (outputs) outputs physical memory or port i/o addresses. ads address status (active low; output) indicates that a valid bus cycle definition and address (w/r , d/c , m/io , bhe , ble , and a23Ca1) are being driven at the am386sx/sxl/sxlv microprocessor pins. bus cycles initiated by ads must be terminated by ready . bhe , ble byte enables (active low; outputs) indicate which data bytes of the data bus take part in a bus cycle. busy busy (active low; input) signals a busy condition from a processor extension. busy has an internal pull-up resistor. clk2 clk2 (input) provides the fundamental timing for the am386sx/ sxl/sxlv microprocessor. d15Cd0 data bus (inputs/outputs) inputs data during memory, i/o, and interrupt acknowl- edge read cycles; outputs data during memory and i/o write cycles. d/c data/control (output) a bus cycle definition pin that distinguishes data cy- cles, either memory or i/o, from control cycles which are interrupt acknowledge, halt, and code fetch. error error (active low; input) signals an error condition from a processor extension. error has an internal pull-up resistor. flt float (active low; input) an input which forces all bidirectional and output sig- nals, including hlda, to the three-state condition. flt has an internal pull-up resistor. the pin, if not used, should be disconnected. hlda bus hold acknowledge (active high; output) output indicates that the am386sx/sxl/sxlv micro- processor has surrendered control of its logical bus to another bus master. hold bus hold request (active high; input) input allows another bus master to request control of the local bus. iiben (am386sxlv only) i/o instruction break enable (active low; input) enables the i/o instruction break feature. iiben has a dynamic internal pull-up resistor. the iiben pull-up is active during reset and whenever the signal is not driven active low by the system. intr interrupt request (active high; input) a maskable input that signals the am386sx/sxl/ sxlv microprocessor to suspend execution of the cur- rent program and execute an interrupt acknowledge function. lock bus lock (active low; output) a bus cycle definition pin that indicates that other sys- tem bus masters are not to gain control of the system bus while it is active. m/io memory/io (output) a bus cycle definition pin that distinguishes memory cy- cles from input/output cycles. na next address (active low; input) used to request address pipelining. nc no connect should always be left unconnected. connection of an nc pin may cause the processor to malfunction or be incompatible with future steppings of the am386sx/ sxl/sxlv microprocessor. nmi non-maskable interrupt request (active high; input) a non-maskable input that signals to the am386sx/ sxl/sxlv microprocessor to suspend execution of the current program and execute an interrupt acknowledge function. pereq processor extension request (active high; input) indicates that the processor has data to be transferred by the am386sx/sxl/sxlv microprocessor. pereq has an internal pull-down resistor.
final am386sx/sxl/sxlv microprocessors data sheet 11 ready bus ready (active low; input) terminates the bus cycle initiated by ads . reset reset (active high; input) suspends any operation in progress and places the am386sx/sxl/sxlv microprocessor in a known reset state. smi (am386sxlv only) system management interrupt (active low; i/o) a non-maskable interrupt pin that signals to the am386sxlv microprocessor to suspend execution and enter system management mode. smi has an in- ternal pull-up resistor. smi has a dynamic internal pull-up resistor that is disabled when the processor is in smm. smi is not three-stated during hold acknowl- edge bus cycles. smiads (am386sxlv only) smi address status (active low; output) when active, this pin indicates that a valid bus cycle definition and address (w/r , d/c , m/io , bhe , ble , and a23Ca1) are being driven at the am386sxlv mi- croprocessor pins while in the system management mode. bus cycles initiated by smiads must be termi- nated by smirdy . smirdy (am386sxlv only) smi ready (active low; input) this input terminates the current bus cycle to the smm mode address space in the same manner the ready pin does for the normal mode address space. smirdy has an internal pull-up resistor. ready and smirdy must not be tied together. v cc system power (input) provides the 5 v nominal dc supply input. v ss system ground (input) provides the 0-v connection from which all inputs and outputs are measured. w/r write/read (output) a bus cycle definition pin that distinguishes write cycles from read cycles. logic symbol 23 2 16 hold hlda error nmi lock na intr pereq ready reset ads clk2 d/c d15Cd0 ble , bhe a23Ca1 m/io bus arbitration control w/r busy data bus interrupt control math coprocessor control bus cycle definition bus cycle control address bus 2x clock 16305cC003 flt float smirdy system management control* mode smiads smi iiben am386sxlv microprocessor *on am386sxlv only
12 am386sx/sxl/sxlv microprocessors data sheet final absolute maximum ratings storage temperature ....................... C65 c to +150 c ambient temperature under bias .... C65 c to +125 c stresses above those listed may cause permanent damage to the device. functionality at or above these limits is not implied. exposure to absolute maxi- mum rating conditions for extended periods may af- fect device reliability. operating ranges supply voltage with respect to v ss ..... C0.5 v to +7.0 v voltage on other pins................ C0.5 v to (v cc +0.5) v operating ranges define those limits between which the functionality of the device is guaranteed. dc characteristics over commercial operating ranges for 25 mhz am386sxlv v cc =3.0 v to 3.6 v; t case =0 c to +100 c v ih input high voltage 2.0 v cc +0.3 v v il input low voltage (note 1) C0.3 +0.8 v c clk clk2 capacitance f c = 1 mhz (note 4) 20 pf c out output capacitance f c = 1 mhz (note 4) 12 pf c in input or i/o capacitance f c = 1 mhz (note 4) 10 pf i ccsb standby current (note 8) i ccsb typ = 10 a150 m a v oh output high voltage i oh = 0.1 ma: a23Ca1, d15Cd0 (note 5) v cc C0.2 v i oh = 0.1 ma: bhe , ble , w/r , d/c , smiads , (note 6) v cc C0.2 v lock , ads , m/io , hlda, smi i oh = 0.5 ma: a23Ca1, d15Cd0 v cc C0.45 v i oh = 0.5 ma: bhe , ble , w/r , d/c , smiads ,v cc C0.45 v lock , ads , m/io , hlda, smi i li input leakage current (all pins except 0 v v in v cc pereq, busy , error , smi , smirdy , (note 7) 10 m a flt , iiben ) v ol output low voltage i ol = 0.5 ma: a23Ca1, d15Cd0 (note 5) 0.2 v i ol = 0.5 ma: bhe , ble , w/r , d/c , smiads ,0.2v m/io , lock , ads , hlda, smi i ol = 2 ma: a23Ca1, d15Cd0 0.45 v i ol = 2.5 ma: bhe , ble , w/r , d/c , smiads ,0.45v lock , ads , m/io , hlda, smi symbol parameter description notes min max unit v ilc clk2 input low voltage (note 1) C 0.3 +0.8 v v ihc clk2 input high voltage 2.4 v cc +0.3 v i ih input leakage current v ih = v cc C0.1 v 300 m a (pereq pin) v ih = 2.4 v (note 2) 200 m a i il input leakage current v il = 0.1 v C300 m a (busy , error , smi , smirdy , flt , iiben ) v il = 0.45 v (note 3) C200 m a i lo output leakage current 0.1 v v out v cc + 15 m a i cc supply current (note 8) v cc = 3.3 v v cc = 3.6 v clk2 = 50 mhz: oper. freq. 25 mhz i cc typ = 95 115 ma final notes: 1. the min value, C0.3, is not 100% tested. 2. pereq input has an internal pull-down resistor. 3. busy , error , flt , smi , iiben , and smirdy inputs each have an internal pull-up resistor. 4. not 100% tested. 5. outputs are cmos and will pull rail-to-rail if the load is not resistive. 6. v oh smi only valid on smi output when exiting smm for two clk2 periods. 7. smi and iiben leakage low will be i li when pull-up is inactive and i il when pull-up is active. 8. inputs at rails (v cc or v ss ).
final am386sx/sxl/sxlv microprocessors data sheet 13 absolute maximum ratings storage temperature ....................... C65 c to +150 c ambient temperature under bias .... C65 c to +125 c stresses above those listed may cause permanent damage to the device. functionality at or above these limits is not implied. exposure to absolute maxi- mum rating conditions for extended periods may af- fect device reliability. operating ranges supply voltage with respect to v ss .... C0.5 v to +7.0 v voltage on other pins................C0.5 v to (v cc +0.5) v operating ranges define those limits between which the functionality of the device is guaranteed. dc characteristics over commercial and industrial operating ranges 25 and 33 mhz: v cc = 5 v 10%; t case = 0 c to +100 c (commercial); t case = C40 c to +100 c (industrial) 40 mhz: v cc = 5 v 5%; t case = 0 c to +100 c i cc supply current (note 8) v cc typ = 5.0 v v cc = 5.5 v clk2 = 50 mhz: oper. freq. 25 mhz i cc typ = 160 190 ma clk2 = 66 mhz: oper. freq. 33 mhz i cc typ = 210 245 ma clk2 = 80 mhz: oper. freq. 40 mhz i cc typ = 255 295 ma c in input or i/o capacitance f c = 1 mhz (note 4) 10 pf c clk clk2 capacitance f c = 1 mhz (note 4) 20 pf c out output or i/o capacitance f c = 1 mhz (note 4) 12 pf i li input leakage current (all pins except 0 v v in v cc pereq, busy , error , sm i*, smirdy *, (note 7) 15 m a flt , and iiben *) v ol output low voltage i ol = 4 ma: a23 C a1, d15 C d0 (note 5) 0.45 v i ol = 5 ma: bhe , ble ,w/r , d/c , smiads *, 0.45 v m/io , lock , ads , hlda, smi * v il input low voltage (note 1) C 0.3 +0.8 v symbol parameter description notes min max unit v ih input high voltage 2.0 v cc +0.3 v v ilc clk2 input low voltage (note 1) C 0.3 +0.8 v v ihc clk2 input high voltage 2.7 v cc +0.3 v i ih input leakage current (pereq pin) v ih = 2.4 v (note 2) 200 m a i il input leakage current (busy , error , smi *, smirdy *, flt , iiben *) v il = 0.45 v (note 3) C 400 m a i lo output leakage current: am386sx/sxl 0.1 v v out v cc 15 m a am386sxlv 0.45 v v out v cc 15 m a i ccsb standby current (note 8) i ccsb typ = 20 m a 150 m a notes: * on am386sxlv only 1. the min value, C0.3, is not 100% tested. 2. pereq input has an internal pull-down resistor. 3. busy , error , flt , smi * , iiben * , and smirdy * inputs each have an internal pull-up resistor. 4. not 100% tested. 5. outputs are cmos and will pull rail-to-rail if the load is not resistive. 6. v oh smi only valid on smi output when exiting smm for two clk2 periods (on am386sxlv only). 7. smi and iiben leakage low will be i li when pull-up is inactive and i i l when pull-up is active (on am386sxlv only). 8. inputs at rails (v cc or v ss ), outputs unloaded, pereq low, error high, busy high, and flt high. final v oh output high voltage i oh = 1.0 ma: a23 C a1, d15 C d0 (note 5) 2.4 v i oh = 0.2 ma: a23 C a1, d15 C d0 v cc C 0.5 v i oh = 0.9 ma: bhe , ble , w/r , d/c , smiads *, (note 6*) 2.4 v lock , ads , m/io , hlda, smi * i oh = 0.18 ma: bhe , ble , w/r , d/c , smiads *, v cc C 0.5 v lock , ads , m/io , hlda, smi *
14 am386sx/sxl/sxlv microprocessors data sheet final switching characteristics the switching characteristics given consist of output delays, input setup requirements, and input hold re- quirements. all switching characteristics are relative to the clk2 rising edge crossing the 2.0-v level. switching characteristic measurement is defined in figure 2. inputs must be driven to the voltage levels in- dicated by figure 2 when switching characteristics are measured. output delays are specified with minimum and maximum limits measured, as shown. the mini- mum delay times are hold times provided to external circuitry. input setup and hold times are specified as minimums, defining the smallest acceptable sampling window. within the sampling window, a synchronous input signal must be stable for correct operation. outputs ads , w/r , d/c , m/io , lock , bhe , ble , a23Ca1, hlda, and smiads * only change at the be- ginning of phase one. d15Cd0 and smi * write cycles only change at the beginning of phase two. the ready , hold, busy , error , pereq, flt , d15C d0, iiben *, and smirdy * read cycles inputs are sam- pled at the beginning of phase one. the na , intr, nmi, and smi * inputs are sampled at the beginning of phase two. * C on am386sxlv only; nc on am386sx/sxl figure 2. drive levels and measurement points for switching characteristics b a valid output n valid output n+1 d c valid input b a valid output n valid output n+1 d c valid input max min max min 2 v clk2 (a23Ca1, bhe , ble , ads , m/io , d/c , w/r , lock , hlda, smiads *) (na , intr, nmi, smi *) (ready , hold, flt , error , busy , pereq, d15Cd0, iiben *, smirdy *) legend: aCmaximum output delay characteristic bCminimum output delay characteristic cCminimum input setup characteristic dCminimum input hold characteristic tx 2 1 f f 16305cC003 (d15Cd0, smi *) notes: 1. input waveforms have tr 2.0 ns from 0.8 vC2.0 v (on am386sxlv only). 2. on am386sx/sxl, v t = 1.5; on am386sxlv, v t = 1.0 v for v cc 3.6 v and 1.5 v for v cc > 3.6 v. 3. * = on am386sxlv only. v t v t v t v t v t v t v t v t
final am386sx/sxl/sxlv microprocessors data sheet 15 switching characteristics over commercial and industrial operating ranges at 25 mhz v cc = 5.0 v 10%; t case = 0 c to +100 c (commercial); t case = C40 c to +100 c (industrial) v cc = 3.0 vC5.5 v; t case = 0 c to +100 c (am386sxlv only) symbol parameter description notes ref. figures final unit min max operating frequency: am386sx cpu am386sxl/sxlv cpu half clk2 freq. half clk2 freq. 2 0 25 25 mhz 1 clk2 period 3, 4 20 ns 2 clk2 high time: am386sxlv cpu at v ihc 34 ns 2a clk2 high time: am386sx/sxl cpu at 2 v 4 7 ns 2b clk2 high time: am386sx/sxl cpu at (v cc C0.8 v) 4 4 ns 3 clk2 low time: am386sxlv cpu at 0.8 v 3 5 ns 3a clk2 low time: am386sx/sxl cpu at 2 v 4 7 ns 3b clk2 low time: am386sx/sxl cpu at 0.8 v 4 5 ns 4 clk2 fall time: am386sx/sxl cpu am386sxlv cpu (v cc C0.8 v) to 0.8 v (note 3) 2.4 v to 0.8 v (note 3) 4 3 7ns 5 clk2 rise time: am386sx/sxl cpu am386sxlv cpu 0.8 v to 2.4 v (note 3) 0.8 v to (v cc C0.8 v) (note 3) 4 3 7ns 6 a23Ca1 valid delay c l = 50 pf 8 4 17 ns 7 a23Ca1 float delay (note 1) 15 4 30 ns 8bhe , ble , lock valid delay c l = 50 pf 8 4 17 ns 9bhe , ble , lock float delay (note 1) 15 4 30 ns 10 m/io , d/c , w/r , ads valid delay c l = 50 pf 8 4 17 ns 10s smiads valid delay c l = 50 pf (note 5) 8 4 25 ns 11 w/r , m/io , d/c , ads float delay (note 1) 15, 18 4 30 ns 11s smiads float delay (notes 1, 5) 15 4 30 ns 12 d15Cd0 write data valid delay c l = 50 pf 8, 9 7 23 ns 12a d15Cd0 write data hold time c l = 50 pf 10 2 ns 13 d15Cd0 write data float delay (note 1) 15 4 22 ns 14 hlda valid delay c l = 50 pf 8 4 22 ns 14f hlda float delay: am386sx/sxl am386sxlv (notes 1, 4) 15, 16 4 4 22 30 ns 15 na setup time 75 ns 16 na hold time 73 ns 19 ready setup time 7 9 ns 19s smirdy setup time (note 5) 7 9 ns 20 ready hold time 7 4 ns 20s smirdy hold time (note 5) 7 4 ns 21 d15Cd0 read data setup time 7 7 ns 22 d15Cd0 read data hold time 7 5 ns 23 hold setup time 7 9 ns 24 hold hold time 7 3 ns 25 reset setup time 17 8 ns 26 reset hold time 17 3 ns 27 nmi, intr setup time (note 2) 7 6 ns 27s smi setup time (note 5) 7 6 ns 28 nmi, intr hold time (note 2) 7 6 ns 28s smi hold time (note 5) 7 4 ns 29 pereq, error , busy , flt , iiben 5 setup time (note 2) 7 6 ns 30 pereq, error , busy , flt , iiben 5 hold time (note 2) 7 5 ns 31 smi valid delay (note 5) 8, 15 4 22 ns 32 smi float delay (notes 1, 4, 5) 16 4 30 ns notes: 1. float condition occurs when maximum output current becomes less than i lo in magnitude. float delay is not 100% tested. 2. these inputs are allowed to be asynchronous to clk2. the setup and hold specifications are given for testing purposes, to assure recognition within a specific clk2 period. 3. rise and fall times are not tested. they are guaranteed by design characterization. 4. only during flt assertion. 5. on am386sxlv only.
16 am386sx/sxl/sxlv microprocessors data sheet final switching characteristics over commercial operating ranges at 33 mhz v cc = 5.0 v 10%; t case = 0 c to +100 c symbol parameter description notes ref. figures final unit min max operating frequency: am386sx cpu am386sxl cpu half clk2 freq. half clk2 freq. 2 0 33 33 mhz 1 clk2 period 415 ns 2a clk2 high time at 2 v 4 6.25 ns 2b clk2 high time at 3.7 v 4 4 ns 3a clk2 low time at 2 v 4 6.25 ns 3b clk2 low time at 0.8 v 4 4.5 ns 4 clk2 fall time 3.7 v to 0.8 v (note 3) 4 4 ns 5 clk2 rise time 0.8 v to 3.7 v (note 3) 4 4 ns 6 a23Ca1 valid delay c l = 50 pf 8 4 15 ns 7 a23Ca1 float delay (note 1) 15 4 20 ns 8bhe , ble , lock valid delay c l = 50 pf 8 4 15 ns 9bhe , ble , lock float delay (note 1) 15 4 20 ns 10 m/io , d/c , w/r , ads valid delay c l = 50 pf 8 4 15 ns 11 w/r , m/io , d/c , ads float delay (note 1) 15 4 20 ns 12 d15Cd0 write data valid delay c l = 50 pf 8 7 23 ns 12a d15Cd0 write data hold time c l = 50 pf 10 2 ns 13 d15Cd0 write data float delay (note 1) 15 4 17 ns 14 hlda valid delay c l = 50 pf 8 4 20 ns 14f hlda float delay 15 4 20 ns 15 na setup time 75 ns 16 na hold time 72 ns 19 ready setup time 7 7 ns 20 ready hold time 7 4 ns 21 d15Cd0 read data setup time 7 5 ns 22 d15Cd0 read data hold time 7 3 ns 23 hold setup time 7 9 ns 24 hold hold time 7 2 ns 25 reset setup time 17 5 ns 26 reset hold time 17 2 ns 27 nmi, intr setup time (note 2) 7 5 ns 28 nmi, intr hold time (note 2) 7 5 ns 29 pereq, error , busy setup time (note 2) 7 5 ns 30 pereq, error , busy hold time (note 2) 7 4 ns notes: 1. float condition occurs when maximum output current becomes less than i lo in magnitude. float delay is not 100% tested. 2. these inputs are allowed to be asynchronous to clk2. the setup and hold specifications are given for testing purposes, to assure recognition within a specific clk2 period. 3. rise and fall times are not tested. they are guaranteed by design characterization. 4. min time is not 100% tested.
final am386sx/sxl/sxlv microprocessors data sheet 17 switching characteristics over commercial operating ranges at 40 mhz v cc = 5.0 v 5%; t case = 0 c to +100 c (am386sx only) symbol parameter description notes ref. figures final unit min max operating frequency half clk2 frequency 2 40 mhz 1 clk2 period 5 12.5 250 ns 2 clk2 high time at 2.7 v 5 4.5 ns 3 clk2 low time at 0.8 v 5 4.5 ns 4 clk2 fall time 2.7 v to 0.8 v (note 3) 5 4 ns 5 clk2 rise time 0.8 v to 2.7 v (note 3) 5 4 ns 6 a23Ca1 valid delay c l = 50 pf 8 4 13 ns 7 a23Ca1 float delay (note 1) 15 4 20 ns 8bhe , ble , lock valid delay c l = 50 pf 8 4 13 ns 9bhe , ble , lock float delay (note 1) 15 4 20 ns 10 m/io , d/c , w/r , ads valid delay c l = 50 pf 8 4 13 ns 11 w/r , m/io , d/c , ads float delay (note 1) 15 4 20 ns 12 d15Cd0 write data valid delay c l = 50 pf (note 4) 8 7 18 ns 12a d15Cd0 write data hold time c l = 50 pf 10 2 ns 13 d15Cd0 write data float delay (note 1) 15 4 17 ns 14 hlda valid delay c l = 50 pf 15 4 17 ns 14f hlda float delay 15 4 17 ns 15 na setup time 75 ns 16 na hold time 72 ns 19 ready setup time 7 7 ns 20 ready hold time 7 4 ns 21 d15Cd0 read data setup time 7 4 ns 22 d15Cd0 read data hold time 7 3 ns 23 hold setup time 7 4 ns 24 hold hold time 7 2 ns 25 reset setup time 17 4 ns 26 reset hold time 17 2 ns 27 nmi, intr setup time (note 2) 7 5 ns 28 nmi, intr hold time (note 2) 7 5 ns 29 pereq, error , busy, flt setup time (note 2) 7 5 ns 30 pereq, error , busy, flt hold time (note 2) 7 4 ns notes: 1. float condition occurs when maximum output current becomes less than i lo in magnitude. float delay is not 100% tested. 2. these inputs are allowed to be asynchronous to clk2. the setup and hold specifications are given for testing purposes, to assure recognition within a specific clk2 period. 3. rise and fall times are not tested. they are guaranteed by design characterization. 4. min time is not 100% tested.
18 am386sx/sxl/sxlv microprocessors data sheet final 16305cC004 t1 t2 t5 v ihc 2.0 v 0.8 v clk2 t3 t4 figure 3. clk2 timing (am386sxlv 25 mhz) 15022b-031 t1 t2b t5 v cc C 0.8 v 2.0 v 0.8 v clk2 t3b t4 figure 4. clk2 timing (am386sx/sxl 25 and 33 mhz) t3a t2a 15022b-031a t1 t2 t5 2.0 v 0.8 v clk2 t3 t4 figure 5. clk2 timing (am386sx 40 mhz) v cc C 0.8 v am386sx/sxl/sxlv cpu output c l 15022bC032 figure 6. ac test circuit
final am386sx/sxl/sxlv microprocessors data sheet 19 switching waveforms t19, t19s* t20, t20s* t23 t24 t21 t22 t29 t30 t15 t16 t27, t27s* t28, t28s* tx tx tx 2121 clk2 hold d15Cd0 na ffff busy , error , iiben *, pereq, flt smi *, intr, nmi ready , smirdy * figure 7. input setup and hold timing * C on am386sxlv only (inputs)
20 am386sx/sxl/sxlv microprocessors data sheet final min tx 2121 clk2 a23Ca1 max valid n valid n+1 t10, t10s* min max valid n valid n+1 t6 min max valid n valid n+1 bhe + , ble + be3 Cbe0 *, lock w/r , m/io , d/c , ads , smiads * t8 ffff d15Cd0 t12 min max valid n+1 smi * t31 min max valid n valid n+1 valid n figure 8. output valid delay timing + C on am386sx/sxl only * C on am386sxlv only (outputs) hlda +
final am386sx/sxl/sxlv microprocessors data sheet 21 figure 9. write data valid delay timing clk2 w/r d15Cd0 valid n t12 min max t1 f 1 f 2 13605cC007 figure 10. write data hold timing clk2 w/r d15Cd0 t12a min f 1 f 2 t1 valid n 16305cC008
22 am386sx/sxl/sxlv microprocessors data sheet final clk2 reset clk (internal) busy ads na d15Cd0 bhe , ble , w/r , m/io , hlda ready low high high during reset during reset during reset up to 30 clk2 up to 30 clk2 up to 30 clk2 reset cycle 1 non-pipelined (read) 1 2 3 17 18 19 395 396 397 398 2 1121212 t1 t2 valid 1 valid 1 (note 1) low to begin self-test (note 2) approximately no self-test error *** * * 16305cC009 2 f f ffff ff f smi notes: 1. busy should be held stable for eight clk2 periods before and after the clk2 period in which the reset falling edge occurs. 2. if self-test is requested, the am386sxlv microprocessor outputs remain in their reset state as shown here. a23Ca1, d/c , lock figure 11. bus activity from reset until first code fetch (am386sxlv only) 3 15 clk2 duration if not going to request self-test. 3 80 clk2 duration before requesting self-test. if self-test is performed, add (2 20 ) + 60* to these numbers. internal initialization negated to allow sensing of a 387dx math coprocessor asserted to indicate 387dx math coprocessor protocol (floating)
final am386sx/sxl/sxlv microprocessors data sheet 23 clk2 control data address reset valid valid valid flt figure 12. entering and exiting flt (am386sxlv only) smi 16306bC008 f 1 f 1 f 1 f 1 f 1 f 1 f 1 f 1 f 1 f 1 valid clk2 smi smiads f 1 f 1 f 1 f 1 f 1 f 1 f 1 smm in progress drive released by cpu system may initiate another smi when necessary* *once initiated, the system must hold smi low until the first smiads . at this time, the system cannot drive smi until three clk2 cycles after the cpu drives smi high. (the cpu will drive smi high for two clk2 cycles. the additional clock allows the cpu to completely release smi and prevents any driver overlap.) cpu driving smi system control of smi 16306bC011 figure 13. initiating and exiting smm (am386sxlv only) clk2 smi reset f 2 f 2 smm in progress cpu drives smi high for two clk2 cycles 6C8 clocks after reset is asserted. 16306bC010 figure 14. reset and smi (am386sxlv only)
24 am386sx/sxl/sxlv microprocessors data sheet final t9 t8 min max min max (high z) t11, t11s* t10, t10s* min max min max (high z) t7 t6 min max min max (high z) t13 t12 min max min max (high z) t13also applies to data float when write cycle is followed by read or idle t14f t14 min max min max clk2 a23Ca1 d15Cd0 hlda bhe , ble , lock w/r , m/io , d/c , ads , smiads * th 2121 2 ti or t1 ffff f t31 min max valid 0 valid 1 valid 2 smi * cycle 0 cycle 1 cycle 2 figure 15. output float delay and hlda and smi * valid delay timing * C on am386sxlv only
final am386sx/sxl/sxlv microprocessors data sheet 25 t9 t8 min max min max (high z) t11, t11s t10, t10s min max min max (high z) t7 t6 min max min max (high z) t13 t12 min max min max (high z) clk2 a23Ca1 d15Cd0 hlda bhe , ble , lock w/r , m/io , d/c , ads , smiads th 2121 2 ti or t1 ffff f smi t14f t14 min max min max (high z) t32 t31 min max min max (high z) 16305cC012 figure 16. output float delay entering and exiting flt (am386sxlv only) t26 t25 clk2 reset 2 or 2 1 12 or1 initialization sequence reset ff ff f f the second internal processor phase following reset high-to-low transition (provided t25 and t26 are met) is f 2. 15021bC084 figure 17. reset setup and hold timing and internal phase
26 am386sx/sxl/sxlv microprocessors data sheet final nom + 6 nom + 3 nom nom C3 nom C6 nom C9 50 75 100 125 150 c l (picofarads) note: this graph will not be linear outside the c l range shown. output valid delay (ns) 15021bC079 figure 18. typical output valid delay versus load capacitance at maximum operating temperature (c l =120 pf) nom + 9 nom + 6 nom + 3 nom nom C3 nom C6 75 100 125 150 c l (picofarads) figure 19. typical output valid delay versus load capacitance at maximum operating temperature (c l =75 pf) note: this graph will not be linear outside the c l range shown. output valid delay (ns) 15021bC080
final am386sx/sxl/sxlv microprocessors data sheet 27 nom + 9 nom + 6 nom + 3 nom nom C3 50 75 100 125 150 c l (picofarads) figure 20. typical output valid delay versus load capacitance at maximum operating temperature (c l =50 pf) output valid delay (ns) note: this graph will not be linear outside the c l range shown. 15021bC081 8 6 4 2 8 50 75 100 125 150 c l (picofarads) figure 21. typical output rise time versus load capacitance at maximum operating temperature note: this graph will not be linear outside the c l range shown. rise time (ns) 0.8 v C 2.0 v 15021bC082
28 am386sx/sxl/sxlv microprocessors data sheet final differences between the am386sx/sxl/sxlv and am386dx/dxl cpu the following are the major differences between the am386sx/sxl/sxlv and the am386dx/dxl cpu. for brevity, throughout this section the am386sx/sxl/ sxlv cpu is referred to as the sx cpu, and the am386dx/dxl cpu is referred to as the dx cpu. n the sx cpu generates byte selects on bhe and ble (like the 8086 and 80286) to distinguish the upper and lower bytes on its 16-bit data bus. the dx cpu uses four byte selects, be3 Cbe0 , to distin- guish between the different bytes on its 32-bit bus. n the sx cpu has no bus sizing option. the dx cpu can select between either a 32-bit bus or a 16-bit bus by use of the bs16 input. the sx cpu has a 16-bit bus size. n the na pin operation in the sx cpu is identical to that of the na pin on the dx cpu with one excep- tion: the dx cpu na pin cannot be activated on 16- bit bus cycles (where bs16 is low in the dx cpu case), whereas na can be activated on any sx cpu bus cycle. n the contents of all sx cpu registers at reset are identical to the contents of the dx cpu registers at reset, except for the dx register. the dx register contains a component-stepping identifier at reset, that is: C in the dx cpu, after reset: dh = 3 indicates dx cpu di = revision number C in the sx cpu, after reset: dh = 23h indicates sx cpu dl = revision number n the dx cpu uses a31 and m/io as selects for the math coprocessor. the sx cpu uses a23 and m/io as selects. n the dx cpu prefetch unit fetches code in four-byte units. the sx cpu prefetch unit reads two bytes as one unit (like the 80286). in bs16 mode, the dx cpu takes two consecutive bus cycles to complete a prefetch request. if there is a data read or write re- quest after the prefetch starts, the dx cpu will fetch all four bytes before addressing the new request. n both the dx cpu and sx cpu have the same log- ical address space. the only difference is that the dx cpu has a 32-bit physical address space and the sx cpu has a 24-bit physical address space. the sx cpu has a physical memory address space of up to 16 mbyte instead of the 4 gbyte available to the dx cpu. therefore, in sx cpu systems, the operating system must be aware of this physical memory limit and should allocate memory for appli- cations programs within this limit. if a dx cpu sys- tem uses only the lower 16 mbyte of physical address, then there will be no extra effort required to migrate dx cpu software to the sx cpu. any application which uses more than 16 mbyte of memory can run on the sx cpu, if the operating system utilizes the sx cpus paging mechanism. in spite of this difference in physical address space, the sx cpu and the dx cpu can run the same op- erating systems and applications within their re- spective physical memory constraints. n the sx cpu has an input called flt , which three- states all bi-directional and output pins, including hlda, when asserted. it is used with on-circuit emulation (once).
final am386sx/sxl/sxlv microprocessors data sheet 29 package thermal specifications the am386sx/sxl/sxlv processors are specified for operation when t case (the case temperature) is within the range of 0 c to +100 c for commercial parts, and C40c to +100c for industrial parts. t case can be mea- sured in any environment to determine whether the am386sx/sxl/sxlv processors are within the speci- fied operating range. the case temperature should be measured at the center of the top surface opposite the pins. the ambient temperature (t a ) is guaranteed as long as t case is not violated. the ambient temperature can be calculated from q jc and q ja and from these equations: t j = t case + p ? q jc t a = t j C p ? q ja t case = t a + p ? [ q ja C q jc ] where: t j , t a , t case = junction, ambient, and case temperature q jc , q ja = junction-to-case and junction-to-ambient thermal resistance, respectively p = maximum power consumption in the 100-lead pqfp package, q ja =45.0 and q jc =11.0. electrical specifications the am386sx/sxl/sxlv cpu has modest power re- quirements. however, its high clock frequency and 47 output buffers (address, data, control, and hlda) can cause power surges as multiple output buffers drive new signal levels simultaneously. for clean on-chip power distribution at high frequency, 14 v cc and 18 v ss pins separately feed functional units of the am386sx/sxl/sxlv cpu. power and ground connections must be made to all ex- ternal v cc and v ss pins of the am386sx/sxl/sxlv cpu. on the circuit board, all v cc pins should be con- nected on a v cc plane, and v ss pins should be con- nected on a gnd plane. power decoupling recommendations liberal decoupling capacitors should be placed near the am386sx/sxl/sxlv cpu. the am386sx/sxl/ sxlv cpu driving its 24-bit address bus and 16-bit data bus at high frequencies can cause transient power surges, particularly when driving large capacitive loads. low inductance capacitors and interconnects are recommended for best high frequency electrical performance. inductance can be reduced by shorten- ing circuit board traces between the am386sx/sxl/ sxlv cpu and decoupling capacitors as much as pos- sible. resistor recommendations the error , flt , and busy inputs have internal pull- up resistors of approximately 20 kohms, and the pereq input has an internal pull-down resistor of ap- proximately 20 kohms, built into the am386sx/sxl/ sxlv cpu to keep these signals inactive when a 387sx-compatible math coprocessor is not present in the system (or temporarily removed from its socket). in typical designs, the external pull-up resistors shown in table 1 are recommended. however, a particular de- sign may have reason to adjust the resistor values rec- ommended here, or alter the use of pull-up resistors in other ways. other connection recommendations for reliable operation, always connect unused inputs to an appropriate signal level. nc pins should always re- main unconnected. connection of nc pins to v cc or v ss will result in component malfunction or incompati- bility with future steppings of the am386sx/sxl/sxlv cpu. particularly when not using the interrupts or bus hold (as when first prototyping), prevent any chance of spu- rious activity by connecting these associated inputs to gnd: pin signal 40 intr 38 nmi 4hold if not using address pipelining, connect pin 6 (na ) through a pull-up in the range of 20 kohms to v cc . table 1. recommended resistor pull-ups to v cc pin signal pull-up value purpose 16 ads 20 kohms 10% lightly pull ads inactive during am386sx/sxl/sxlv cpu hold acknowledge states. 26 lock 20 kohms 10% lightly pull lock inactive during am386sx/sxl/ sxlv cpu hold acknowledge states.
30 am386sx/sxl/sxlv microprocessors data sheet final physical dimensions pqb 100 (plastic quad flat pack, trimmed and formed) trademarks amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. am386 is a registered trademark; and e86 is a trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies. pin 100 pin 75 pin 50 pin 1 i.d. 16-038-pqb pqb100 db90 3-6-97 lv top view 0.897 0.903 0.747 0.753 0.875 0.885 0.897 0.903 0.008 0.012 pin 25 0.875 0.885 0.747 0.753 0.025 basic 0.160 0.180 0.60 ref bottom view 0.130 0.150 0.020 0.040 seating plane end view 0 0 8 gage plane 0.065 ref 7 typ. 0 min 0.045 x45 chamfer 0.015 0.008 r 0.010 min flat shoulder 0.036 0.046 7 typ. 0.010

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